1. Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to a semiconductor memory comprising a memory unit comprising a plurality of memory blocks, and a bypass metal interconnection layer for propagation of various signals for reading out data to each of the memory blocks.
2. Description of the Prior Art
Conventionally, as one example of a semiconductor memory, an AND type semiconductor memory which is integrated in a semiconductor chip has been known. More specifically, an AND type read-only memory (referred to as D-A-ROM hereinafter) employing a depletion type transistor has been actually used. Such a type of semiconductor memory is disclosed in detail, for example, by S. Kouyama et al. in "Very High Speed MOS Device", Baifukan, the Japanese publication issued on Feb. 10, 1986.
FIG. 1 is a block diagram showing schematically the environment in which such a conventional D-A-ROM is used. More specifically, in FIG. 1, a CPU 100 in a microcomputer applies to a D-A-ROM 200 a read control signal RD and three kinds of address information A.sub.X, A.sub.Y and A.sub.Z at predetermined timing at the time of reading out data. The D-A-ROM 200 is responsive to the signals for applying to the CPU 100 data read out from a contained memory unit (not shown).
FIG. 2 is a block diagram showing structure of the above described D-A-ROM 200. More specifically, FIG. 2 shows the layout of the D-A-ROM employed in an 8-bit microcomputer "M50740-XXXP" manufactured by Mitsubishi Electric Corporation.
Referring now to FIG. 2, the conventional D-A-ROM will be described. In FIG. 2, the three kinds of address information A.sub.X, A.sub.Y and A.sub.Z sent from the CPU 100 are applied to a block address decoder (X decoder) 2, a block decoder (Y decoder) 1 and a column selector 3, respectively. In addition, a memory unit 4, which comprises n memory block 4 - 1, 4 - 2, . . . , 4 - n defines J-bit data in response to designation by the X decoder 2 and the Y decoder 1.
More specifically, the Y decoder 1 is responsive to the address information A.sub.Y from the CPU 100 for generating signals Y.sub.1, Y.sub.2, . . . , Y.sub.n for selecting a particular memory block to read out data out of one of the n memory blocks 4 - 1, 4 - 2, . . . , 4 - n. The Y decoder outputs the signals Y.sub.1, Y.sub.2, . . . , Y.sub.n, to output the same to first gate electrode connectors 7. The signals Y.sub.1, Y.sub.2, . . . , Y.sub.n which are propagated through respective first gate electrode connectors layers 7 are applied to the corresponding memory blocks 4 - 1, 4 - 2, . . . , 4 - n, respectively, to be applied in common to particular gates (not shown) of a plurality of AND type memories each constituting each of the memory blocks.
In addition, the X decoder 2 is responsive to the address information A.sub.X from the CPU 100 for generating signals X.sub.1, X.sub.2, . . . , X.sub.m for designating in common a particular row address in each of the memory blocks. The X decoder outputs the signals X.sub.1, X.sub.2, . . . , X.sub.n to second gate electrode connectors 8. The signals X.sub.1, X.sub.2, . . . , X.sub.m are further applied to the second gate electrode connectors 8 of other blocks through connectors 5 in a metal interconnection layer (aluminum interconnection layer). The signals X.sub.1, X.sub.2, . . . , X.sub.m which are propagated through respective second gate electrode connectors 8 are applied in common to predetermined gates (not shown) in each of the memory blocks, so that a particular row address is designated in common in each of the memory blocks.
Furthermore, a read control signal RD is applied to third gate electrode connectors 9 from the CPU 100 through a connector 10 in the metal interconnection layer (aluminum interconnection layer). The first, second and third gate electrode connectors 7, 8 and 9 may all be formed in a single gate interconnector layer. The signal RD which is propagated through each of the third gate electrode connectors layers 9 is applied to predetermined gates (not shown) in each of the memory blocks.
More specifically, J-bit data d.sub.1, d.sub.2, . . . , d.sub.j corresponding to a particular row address designated in response to the signals X.sub.1, X.sub.2, . . . , X.sub.m from the X decoder 2 in a particular memory block selected in response to the signals Y.sub.1, Y.sub.2, . . . , Y.sub.n from the Y decoder 1 are outputted to metal connectors (in the aluminum interconnection layer) each serving as a bit line in response to the read control signal RD applied from the CPU 100.
The column selector 3 is responsive to the address information A.sub.Z from the CPU 100 for reading out data corresponding to a particular column address, to send the same to the CPU 100.
Meanwhile, in the above described conventional D-A-ROM, if the number J of columns which can be read out at a time is increased, interconnection resistance values of the second gate electrode connectors 8 and the third gate electrode connectors 9 are increased, so that additional time is required for reading out data. Thus, in order to drive such gate electrode connectors each having high resistance thereby to surely read out J-bit data from each row, a decoder requires high driving ability. However, such high driving ability causes the power consumption to be substantially increased.